1. Field of the Invention
The present invention relates to a semiconductor device comprising an ESD protection circuit for protecting a circuit from being destructed by electrostatic discharge (to be abbreviated as ESD hereinafter), and more specifically, to a semiconductor device that is connected by use of bumps arranged in a manner of a two-dimensional area.
2. Description of the Related Art
A semiconductor device comprising a conventional ESD protection circuit will now be described.
FIG. 1 is a plan view of a semiconductor device (silicon chip) that is to be connected to an external member by means of a bonding wire.
FIG. 1 shows an ordinary procedure of connecting the silicon chip to an outside member with a bonding wire, and as shown in this figure, a wire 103 is bonded to an input/output pad 102 provided close to an outer circumference of a silicon chip 101. The input/output pad 102 is connected to a functional module 105 formed at a central portion of the silicon chip via an input/output circuit 104. Note that FIG. 1 is a view taken from the surface side where the input/output pad 102 is formed.
The input/output circuit 104 comprises an input/output buffer including an ESD protection circuit, or a power input circuit including an ESD protection circuit. The functional module 105 is a circuit that has a pre-assigned function, which comprises a memory device such as DRAM, or an analog IP (analog intellectual property). When a signal or a power voltage is input from the bonding wire 103 to the device, the ESD protection circuit built in the input/output circuit 104 functions and thus the functional module 105 is protected from ESD.
FIG. 2 is a cross section of a flip chip package that carries out a connection between a semiconductor chip and a package substrate at a bump. FIG. 3 is a plan view of a silicon chip in the above-mentioned flip-flop package, and this view is taken from the surface side on which the bump is formed.
As shown in FIG. 2, a silicon chip 111 is connected onto a package substrate 112 with bumps 113. The silicon chip 111 is connected to balls 114 by the bumps 113, an interconnection layer formed on the package substrate, through-holes and the like. Further, the silicon chip 111 on the package substrate 112 is covered by a cap member 115.
Further, as shown in FIG. 3, in the silicon chip 111 of the flip-flop package, the bumps 113 (including 113A and 113B) are arranged in a two-dimensional manner on a surface of the silicon chip 111. The input/output circuit 116 is formed close to the outer circumference of the silicon chip 111, and a circuit having a pre-assigned function (to be called as functional module) 117 is formed inside the input/output circuit 116.
Here, it should be pointed out that when a silicon chip 111 and a package substrate 112 are connected to each other by means of bumps made by, for example, soldering, instead of bonding wires, as in the case of the flip chip package shown in FIG. 2, the following problem will be created.
That is, in the flip chip package, bumps 13A are formed not only close to the outer circumference of the silicon chip 11, but also bumps 13B are made at positions on an inner side than the input/output circuit 116 and also distant from the circuit 16. With this structure, it is not possible in some cases to transmit a signal inputted to a bump 113B to the functional module 117 provided at a central portion of the silicon chip 111 via the ESD protection circuit formed in the input/output circuit 116.
In particular, such a semiconductor chip in which a DRAM, some other memory, analog IP (analog intellectual property) and the like are mixedly integrated as functional modules, and each of these members has its own exclusive power source, entails the problem that a withstand voltage of the semiconductor chip against ESD is low when each exclusive power is input without being passed through an ESD protection circuit.